Limbo
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Every comparison, measured.

Limbo emits fewer cross-chip 2-qubit operations, the ones that cost ten times an on-chip gate, than Quantinuum's TKET in every comparison we ran. It also compiles a median 118× faster. Every figure on this page is generated from the published benchmark data.

Comparisons won vs TKET
24/24
Largest cut reduction vs TKET
78%
Median compile speedup
118×
Fidelity comparisons won
8/8

Preprint · Zenodo · May 2026

Limbo: A Multi-Chip-First Quantum Compiler Unifying Hypergraph Partitioning with Topological Cross-Chip Routing

Jaymin Ding · Princeton University · doi:10.5281/zenodo.20442129

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Beats TKET in every comparison

TKET is Quantinuum's flagship compiler and the strongest general-purpose baseline available. Both compilers run a full end-to-end compile on the same circuits, and we count the cross-chip operations left in each compiler's final output. Limbo wins all 24, on two different chip topologies, cutting cross-chip operations by up to 78% while compiling up to 2735× faster.

Fully-connected chips

Intra-chip topology: every qubit can talk to every other on the same chip. No SWAPs needed within a chip; only cross-chip routing has real cost. This matches the model Limbo's partitioner is built on, and the one most trapped-ion architectures actually deliver.

Limbo wins
12/12
Average cut reduction
35%
Largest single comparison
58%
Workload n Limbo cuts TKET cuts Limbo as share of TKET Limbo s TKET s Speedup
QFT 32 324 472 −31% 0.9 15.54 17×
QFT 64 1028 1482 −31% 0.78 44.69 58×
IQFT 32 334 450 −26% 0.38 15.22 40×
IQFT 64 920 1474 −38% 0.43 44.13 102×
QAOA MaxCut 32 248 344 −28% 0.35 10.66 31×
QAOA MaxCut 64 1672 1944 −14% 0.33 46.19 140×
Random Clifford+T 32 50 120 −58% 0.14 6.66 48×
Random Clifford+T 64 204 421 −52% 0.23 15.64 68×
Sparse Random 32 66 125 −47% 0.2 5.79 30×
Sparse Random 64 202 416 −51% 0.17 14.16 84×
Asymmetric Hotspot 32 127 148 −14% 0.24 8.59 35×
Asymmetric Hotspot 64 429 654 −34% 0.18 21.59 119×

Constrained chips (2-D nearest-neighbor)

Intra-chip topology: 4×5 nearest-neighbor grid. Both compilers now have to insert real SWAPs even within a chip. This is the strictest realistic apples-to-apples comparison: the layout superconducting hardware sees.

Limbo wins
12/12
Average cut reduction
47%
Largest single comparison
78%
Workload n Limbo cuts TKET cuts Limbo as share of TKET Limbo s TKET s Speedup
QFT 32 324 500 −35% 0.13 17.64 140×
QFT 64 1028 1558 −34% 0.28 53.63 192×
IQFT 32 326 538 −39% 0.13 18.95 143×
IQFT 64 904 1614 −44% 0.32 55.34 173×
QAOA MaxCut 32 224 424 −47% 0.11 13.63 126×
QAOA MaxCut 64 1676 1980 −15% 0.31 514.48 1654×
Random Clifford+T 32 50 228 −78% 0.1 8.43 83×
Random Clifford+T 64 211 566 −63% 0.17 24.11 144×
Sparse Random 32 66 204 −68% 0.07 7.91 117×
Sparse Random 64 208 441 −53% 0.1 275.93 2735×
Asymmetric Hotspot 32 126 230 −45% 0.11 13.78 130×
Asymmetric Hotspot 64 427 776 −45% 0.2 112.6 563×

Why Limbo wins. It solves the multi-chip problem directly: partition first to minimise cross-chip operations, then give each chip a small, fast routing problem. TKET treats the whole machine as one coupling map and pays for cross-chip hops as it routes. The gap widens on constrained chips, exactly the layout superconducting hardware uses.

Fewer crossings, better answers

Cutting cross-chip operations translates straight into output closer to the correct answer. Under a calibrated multi-chip noise model, with cross-chip gates at 0.050 error against 0.005 on-chip, Limbo's circuits achieve higher fidelity than TKET's in every comparison where fidelity can separate the two compilers, 8 of 8, with gains of up to 6.66 percentage points¹.

Fidelity comparisons won
8/8
Best gain
+6.66 pp
Average gain
+2.54 pp
Workload n Hellinger fidelity Δ pp Limbo 2q TKET 2q Note
QFT 12 Limbo0.8067 TKET0.805 +0.16 132 159 uniform ideal ¹
IQFT 12 Limbo0.8021 TKET0.8054 -0.33 132 159 uniform ideal ¹
QAOA MaxCut 12 Limbo0.6615 TKET0.6474 +1.42 112 136
Random Clifford+T 12 Limbo0.4774 TKET0.4312 +4.61 63 84
Sparse Random 12 Limbo0.6358 TKET0.5692 +6.66 48 88
Asymmetric Hotspot 12 Limbo0.1647 TKET0.1056 +5.91 89 134
QFT 16 Limbo0.1165 TKET0.116 tie 240 282 uniform ideal ¹noise floor ²
IQFT 16 Limbo0.1161 TKET0.116 tie 240 279 uniform ideal ¹noise floor ²
QAOA MaxCut 16 Limbo0.1214 TKET0.1146 +0.69 172 205 noise floor ²
Random Clifford+T 16 Limbo0.1798 TKET0.1315 +4.83 96 137 noise floor ²
Sparse Random 16 Limbo0.127 TKET0.1147 +1.23 69 130 noise floor ²
Asymmetric Hotspot 16 Limbo0.0765 TKET0.0242 +5.23 113 168 noise floor ²

¹ QFT produces a uniform output, so fidelity can't separate the compilers on those rows.

² At 16 qubits both compilers approach the noise floor, and Limbo still leads, reaching about 3× TKET's fidelity on Asymmetric Hotspot.

Ahead of the leading research partitioner

QuPort is a recent research-grade multi-chip partitioner. Across a wider matrix of seven workload families at 16, 32 and 64 qubits, Limbo wins or ties 19 of 21 comparisons, and leaves 71% fewer cross-chip operations than a naïve partition on average.

Fourier

Workload n Limbo QuPort Naïve vs QuPort
QFT 16 0 0.0 192 tie
QFT 32 330 562.0 768 −41%
QFT 64 910 3008.0 3072 −70%
IQFT 16 0 0.0 192 tie
IQFT 32 350 562.0 768 −38%
IQFT 64 1028 3008.0 3072 −66%

Variational

Workload n Limbo QuPort Naïve vs QuPort
QAOA MaxCut 16 0 0.0 128 tie
QAOA MaxCut 32 248 304.0 524 −18%
QAOA MaxCut 64 1632 1836.0 2160 −11%
Hardware-Eff. Ansatz 16 16 0.0 52 fits one chip
Hardware-Eff. Ansatz 32 16 8.0 92 +100%
Hardware-Eff. Ansatz 64 16 16.0 188 tie

Randomized

Workload n Limbo QuPort Naïve vs QuPort
Random Clifford+T 16 0 0.0 121 tie
Random Clifford+T 32 50 75.0 233 −33%
Random Clifford+T 64 209 227.0 437 −8%
Sparse Random 16 0 0.0 85 tie
Sparse Random 32 66 120.0 138 −45%
Sparse Random 64 203 241.0 330 −16%

Application-shaped

Workload n Limbo QuPort Naïve vs QuPort
Asymmetric Hotspot 16 0 0.0 169 tie
Asymmetric Hotspot 32 127 174.0 327 −27%
Asymmetric Hotspot 64 427 501.0 642 −15%

Limbo's lead grows with circuit size and density, which is where multi-chip compilation matters. "Fits one chip" marks workloads too small to need partitioning.

Largest wins against QuPort

QFT (n=64) 910 vs 3008.0 · −70%
IQFT (n=64) 1028 vs 3008.0 · −66%
Sparse Random (n=32) 66 vs 120.0 · −45%
QFT (n=32) 330 vs 562.0 · −41%
IQFT (n=32) 350 vs 562.0 · −38%

Where the gains come from

Three components drive the result.

Partitioner 71% fewer cross-chip operations than a naïve partition, on average across the matrix.
Scheduler 8.5% less total run time than a first-in-first-out scheduler, at 8 links per chip. The advantage grows with link capacity; see the scheduler sweep.
Template cache 100× fewer partitioning passes on a 100-step VQE. Limbo partitions once and reuses it; without a cache, every step partitions again.

Running on real quantum hardware

Limbo's full pipeline (compile, partition, transpile, submit and retrieve) runs end to end on AWS Braket's Rigetti Cepheus-1-108Q, a 108-qubit superconducting QPU.

Workload n Device Shots Hellinger fidelity Status
Sparse Random 12 Cepheus-1-108Q 256 0.0351 completed
Asymmetric Hotspot 12 Cepheus-1-108Q 256 0.0041 completed

At this circuit depth, any compiler's output on today's single-chip hardware is limited by gate noise. These runs show the whole pipeline working end to end on a real device.

Routing on live calibration data

On real hardware, Limbo pulls the device's live per-qubit calibration and steers layout toward its best qubits. On Cepheus-1-108Q it read 102 qubit fidelities and automatically routed around 5 faulty qubits.

Built for what's next. Leading hardware roadmaps point to modular, multi-chip machines. Limbo already runs end to end on real hardware and is ready to target multi-chip systems as they reach the cloud. Until then, its multi-chip results are measured under the calibrated noise model above.

A scheduler that gains as hardware scales

Limbo's critical-path scheduler sequences cross-chip operations through limited link capacity. On a 64-qubit workload across four chips, its advantage grows as link capacity grows.

Ports / QPU FIFO makespan Critical-path makespan Makespan saved Regime
1 295803 295403 0.1% Contention-bound
2 185997 185716 0.2% Mixed
4 136090 128766 5.4% Slack opens
8 120230 110055 8.5% Local-depth bound

As port capacity increases, which is the direction modular hardware is heading, the scheduler saves up to 8.5% of total run time.

Where Limbo fits

Toolkit Partitioner Input frameworks Live topology query Variational streaming
Limbo Mt-KaHyPar + critical-path scheduler Qiskit, Cirq, OpenQASM-3 Yes (IBM / AWS / Azure) Yes
QuPort TPCCAP local search + layered estimator Qiskit only Manual config No
Qiskit transpile (single-chip) SABRE layout + routing Qiskit only Yes (IBM only) Partial (PUBs)
Naïve stripe partition Stripe by qubit index n/a No No

Methods

Setup
Every comparison uses 4 chips × 20 qubits with a fixed random seed. The same circuit goes to each compiler. Cut counts come from each compiler's own output, makespans from each compiler's native estimator, and compile time is wall-clock through the full pipeline.
Baselines
TKET for the end-to-end compile comparison; QuPort and a naïve index-stripe partition for the broader partitioning matrix.
Scope
The TKET matrix covers workloads where multi-chip routing does real work (hardware-efficient ansätze and circuits small enough for one chip are excluded). Multi-chip fidelity is measured under a calibrated noise model, since multi-chip QPUs aren't yet publicly available; the hardware rows are real Braket runs. Queue time and shot cost aren't included.
Reproduce
The runner scripts and the resulting JSON artifacts are in the repository, and every table on this page is rendered from those artifacts.

Read the full paper

The preprint covers the method, the noise model, the ablations and the real-hardware runs. Open it on Zenodo for a wider view.

The canonical record is on Zenodo. If your browser doesn't show PDFs inline, open the PDF directly.

Cite this work

@misc{ding2026limbo,
  author    = {Ding, Jaymin},
  title     = {{Limbo: A Multi-Chip-First Quantum Compiler Unifying
                Hypergraph Partitioning with Topological Cross-Chip
                Routing}},
  year      = {2026},
  month     = may,
  publisher = {Zenodo},
  doi       = {10.5281/zenodo.20442129},
  url       = {https://doi.org/10.5281/zenodo.20442129},
}